The present invention relates to a semiconductor device and more particularly to a method of forming a contact plug in a NAND flash memory device.
In general, semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices include memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), in which the data speed is fast, but data stored therein is lost when power is switched off. In contrast, the nonvolatile memory devices include memory devices in which data stored therein is retained although power is switched off.
A flash memory device is a type of nonvolatile memory device and is a highly-integrated memory device, which was developed by combining the advantages of Erasable Programmable Read Only Memory (EPROM) which can be programmed and erased and Electrically Erasable Programmable Read Only Memory (EEPROM) which can be electrically programmed and erased.
Flash memory devices can be classified into a NOR type flash memory device and a NAND type flash memory device depending on a structure of a cell and operation conditions. In the NOR type flash memory device, a drain of each memory cell transistor is connected to a bit line. Thus, the NOR type flash memory device enables program and erase with respect to a predetermined address and therefore has a fast operating speed. Accordingly, the NOR type flash memory device has generally been used in application fields requiring a high-speed operation. In contrast, in the NAND type flash memory device, a plurality of memory cell transistors are connected in series to form one string. One string is connected between bit lines and a common source line. Thus, the number of drain contact plugs is relatively small, enabling higher integration. Accordingly, the NAND type flash memory device has generally been used in application fields requiring high-capacity data retention.
The NAND type nonvolatile memory device has a plurality of word lines formed between a source select line and a drain select line. Gates of select transistors respectively included in the plurality of strings are interconnected to form the select line, such as the source select line or the drain select line, and gates of memory cell transistors respectively included in the plurality of strings are interconnected to form the word lines. A tunnel oxide layer, a floating gate, a dielectric layer and a control gate are included in the select line and the word lines. In the select line, the floating gate and the control gate are electrically connected. A junction region is formed between the select line and the word lines. At this time, a junction region between the source select lines becomes a source region, and a junction region between the drain select lines becomes a drain region.
A spacer and a Self Align Contact (SAC) nitride film for protecting the sides of the select lines and the word lines are formed on the sides of the select lines and the word lines. A dielectric layer is formed on the entire surface of the select lines and the word lines. A contact hole through which the junction region between the select lines is exposed is formed in the dielectric layer. The contact hole is gap filled with a conductive material, so a contact plug electrically connected to the junction region is formed.
However, as flash memory devices become highly integrated and miniaturized, a space between the select lines where the source contact plug and the drain contact plug are formed is narrowed. Thus, the size of the source contact plug and the drain contact plug is decreased. Accordingly, it becomes an important issue to form metal lines (e.g., bit lines) and contact plugs so that miss alignment between the metal lines and the contact plugs are not generated.